The present invention relates to a semiconductor device, and more specifically, a semiconductor device adopting an SOI (silicon on insulator) structure, which is provided with a capacitor. And the present invention also relates to a method for manufacturing a semiconductor device.
In pace with the great progress achieved in the technical field of semiconductor devices over the years, the need for bringing system LSIs into practical use, achieved by mounting digital circuits and analog circuit together on a single chip has been realized in recent years. In such a system LSI device, it is necessary to create a capacitor structure achieved by overlaying conductive films (e.g., polysilicon, aluminum) with thin oxide films sandwiched in between on a single chip, in addition to a gate structure.
Furthermore, a device having an LSI formed on an SOI wafer mainly in order to achieve a reduction in power consumption and higher speed in the device has been attracting much interest recently. It is to be noted that an SOI wafer refers to a wafer constituted by forming an insulating layer on a substrate and forming a thin silicon layer (SOI layer) on the insulating layer.
A semiconductor device 800 achieving an SOI structure is manufactured through the following manufacturing flow in the prior art.
As illustrated in FIG. 10(a), a pad film 820 is first formed on an SOI layer 808 of an SOI wafer 802, and then an oxidation-preventing film 822 is formed over the pad film 820. Next, as illustrated in FIG. 10(b), the pad film 820 and the oxidation-preventing film 822 are patterned. When the patterning process is completed, the pad film 820 and the oxidation-preventing film 822 are left only over anticipated formation areas 812xe2x80x2, where transistors 812 are to be formed, and they are no longer present over anticipated formation area 810xe2x80x2, in which capacitor 810 is to be formed. Next, as illustrated in FIG. 10(c), a field oxidation is performed by using the patterned oxidation-preventing film 822 as a mask to form isolation regions 814 at the SOI layer 808. In the semiconductor device 800, an isolation region 814 is also formed over the anticipated formation area 810xe2x80x2. Next, as illustrated in FIG. 10(d), a first electrode 810a (120xcx9c200 nm) constituted of conductive polysilicon is formed on the SOI layer 808 located at the anticipated formation area 810xe2x80x2, and then, the surface of the first electrode 810a is oxidized to form a dielectric film 810b (8xcx9c10 nm) to achieve a required capacitance at the capacitor 810. Next, the oxidation-preventing film 822 and the pad film 820 at the anticipated formation areas 812xe2x80x2 are removed. It is to be noted that a suitable photoresist pattern is used to protect the anticipated formation area 810xe2x80x2 to ensure that the dielectric film 810b is not removed during this process. Then, as illustrated in FIG. 10(e), after performing implantation processing that is necessary to form the transistors 812 in active areas 812a, the active areas 812a undergo gate oxidation and a gate insulating film 812b is formed at the active areas 812a. Next, as illustrated in FIG. 10(f), a conductive polysilicon film 826 (120xcx9c200 nm) is formed over the entire surface of the wafer. Then, as illustrated in FIG. 10(g), by patterning the polysilicon film 826, gate electrodes 812c of the transistors 812 and a second electrode 810c of the capacitor 810 are formed out of the polysilicon film 826.
However, in the semiconductor device 800 and the manufacturing method thereof in the prior art described above, the first electrode 810a of the capacitor 810 is formed on the SOI layer 808. As a result, a stage 810axe2x80x2 corresponding to the thickness of the first electrode 810a is formed at the wafer surface when forming the second electrode 810c of the capacitor 810 and the gate electrodes 812c of the transistors 812. This stage 810axe2x80x2 causes degradation in the pattern accuracy during the photolithography process implemented to form the second electrode 810c and the gate electrodes 812c. Since extremely fine control is required for the gate electrode processing accuracy in a method for manufacturing a semiconductor device in the future, the presence of the stage 810axe2x80x2 may prove fatal to the semiconductor device.
It is to be noted that while it is conceivable to form the second electrode of the capacitor and the gate electrodes at the transistors through separate steps, this solution presents a new problem in that the manufacturing process becomes lengthy.
The present invention has been completed by addressing the problems of the semiconductor device and the manufacturing method thereof in the prior art, including the problems discussed above.
Accordingly, the semiconductor device assuming an SOI structure according to the present invention employs a structure having a capacitor provided with a dielectric member, a first electrode contained in an SOI layer and a second electrode facing opposite the first electrode via the dielectric member, and an isolation region that is contained in the SOI layer and electrically isolates the first electrode from the remaining area of the SOI layer. In the semiconductor device employing this structure, the first electrode is contained in the SOI layer. Thus, when forming electrodes and wirings for electrical elements (e.g., transister) excluding the capacitor on the SOI layer, the electrodes and the wirings can be formed on a surface that is essentially the same as the surface on which the second electrode is formed. As a result, the pattern for the electrodes and the wirings can be formed concurrently with the formation of the pattern for the second electrode with a high degree of accuracy.
It is to be noted that according to the present invention, the first electrode of the capacitor may be constituted of silicon doped with a specific impurity or polysilicon doped with a specific impurity, for instance. Alternatively, according to the present invention, the first electrode may be constituted of a metal silicide, such as Co (cobalt) silicide, Ti (titanium) silicide or Mo (molybdenum) silicide.
In addition, according to the present invention, the dielectric member at the capacitor may be constituted of, for instance, silicon oxide.
Furthermore, according to the present invention, the second electrode of the capacitor may be constituted of, for instance, polysilicon doped with a specific impurity. Alternatively, the second electrode may be constituted of a material whose main constituent is a metal such as an Al (aluminum) alloy, W (tungsten) or Cu (copper).
According to the present invention, the second electrode may be formed through, for instance, a combination of photolithography and etching or through the CMP method.
Moreover, according to the present invention, the SOI layer may be either the full depletion type or the partial depletion type. It is to be noted that normally, the threshold voltage can be set lower at a full depletion type SOI layer than the threshold voltage of a partial division type SOI layer which would be set at the same leak current area.
In addition, addressing the problems discussed above, the method for manufacturing a semiconductor device assuming an SOI structure and provided with a capacitor constituted of a first electrode, a dielectric member and a second electrode according to the present invention comprises a first step in which an isolation region to be contained in the SOI layer is formed, a second step in which the first electrode is formed, contained in the SOI layer and electrically isolated from the remaining area of the SOI layer, a third step in which the dielectric member is formed on the first electrode and a fourth step in which the second electrode is formed on the dielectric member facing opposite the first electrode via the dielectric member.
It is to be noted that in the first step, the isolation region may be formed through the LOCOS method.
In addition, a process in which required conductivity is achieved at the SOI layer where the capacitor is to be formed through ion implantation of a specific impurity may be included in the second step.
The second step may otherwise include a process in which the anticipated capacitor formation area at the SOI layer is transformed to polysilicon through ion implantation of an inert element and a process in which required conductivity is achieved at the SOI layer corresponding to the polysilicon anticipated formation area through ion implantation of a specific impurity.
Alternatively, the second step may include a process in which a metal film is formed on the SOI layer over the area where the capacitor is to be formed and a process in which the SOI layer corresponding to the anticipated formation area is reacted with the metal film through a heat treatment to form silicide.
As a further alternative, a step may be included in which a layer insulating film is formed having a pattern that opens over the area where the capacitor is to be formed, to be implemented before the fourth step, and a process in which a metal layer that covers, at least, the anticipated formation area is formed and a process in which the second electrode is formed at the anticipated formation area out of the metal layer through photolithography and etching may be included in the fourth step.
Furthermore, a step may be included in which a layer insulating film is formed having a pattern that opens over the area where the capacitor is to be formed, to be implemented before the fourth step, and a process in which a metal layer that covers, at least, the anticipated formation area and a specific portion of the layer insulating film is formed and a process in which the second electrode is formed at the anticipated formation area and a specific wiring is formed at the specific area out of the metal layer through photolithography and etching may be included in the fourth step.
Moreover, a step may be included in which a layer insulating film is formed having a pattern that opens over the area where the capacitor is to be formed, to be implemented before the fourth step, and a process in which a metal layer that covers, at least, the anticipated formation area is formed and a process in which the second electrode is formed at the anticipated formation area out of the metal layer through CMP may be included in the fourth step.
Alternatively, a step in which a transistor having an active area that is contained in the SOI layer is formed and a step in which a silicon block is formed at the surface of the SOI layer that corresponds to, at least, the upper portion of the active area may be included to be implemented after the second step.
Moreover, a step in which a transistor having an active area that is contained in the SOI layer is formed, a step in which a silicon block is formed at the surface of the SOI layer that corresponds to, at least, the upper portion of the active area and a step in which the silicon block is reacted to form silicide may be included to be implemented after the second step.